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<title>IP Core Generation Report for OFDM_Tx_HW</title>
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<h2 class="title">IP Core Generation Report for OFDM_Tx_HW</h2>
<div>
<h3 class="sectionHeading">Summary</h3>
<table>
<tbody>
<tr>
<td class="distinctCellColor">IP core name
</td>
<td class="summaryTableSndColOddRow">ofdm_tx
</td>
</tr>
<tr>
<td>IP core version
</td>
<td class="summaryTableSndColEvenRow">0.4
</td>
</tr>
<tr>
<td class="distinctCellColor">IP core folder
</td>
<td class="summaryTableSndColOddRow"><a href="matlab:uiopen('hdl_prj\ipcore\ofdm_tx_v0_4\*.*')">hdl_prj\ipcore\ofdm_tx_v0_4</a>
</td>
</tr>
<tr>
<td>IP core zip file name
</td>
<td class="summaryTableSndColEvenRow">ofdm_tx_v0_4.zip
</td>
</tr>
<tr>
<td class="distinctCellColor">Target platform
</td>
<td class="summaryTableSndColOddRow">Generic Xilinx Platform
</td>
</tr>
<tr>
<td>Target tool
</td>
<td class="summaryTableSndColEvenRow">Xilinx Vivado
</td>
</tr>
<tr>
<td class="distinctCellColor">Target language
</td>
<td class="summaryTableSndColOddRow">VHDL
</td>
</tr>
<tr>
<td>Model
</td>
<td class="summaryTableSndColEvenRow"><a class="code2model" id="code2model" href="matlab:Simulink.ID.hilite('OFDM_Tx_HW')">OFDM_Tx_HW</a>
</td>
</tr>
<tr>
<td class="distinctCellColor">Model version
</td>
<td class="summaryTableSndColOddRow">1.307
</td>
</tr>
<tr>
<td>HDL Coder version
</td>
<td class="summaryTableSndColEvenRow">3.16
</td>
</tr>
<tr>
<td class="distinctCellColor">IP core generated on
</td>
<td class="summaryTableSndColOddRow">24-Mar-2022 21:51:02
</td>
</tr>
<tr>
<td>IP core generated for
</td>
<td class="summaryTableSndColEvenRow"><a class="code2model" id="code2model" href="matlab:Simulink.ID.hilite('OFDM_Tx_HW:9873')">OFDMTx</a>
</td>
</tr>
</tbody>
</table>
</div>
<div>
<h3 class="sectionHeading">Target Interface Configuration</h3>
You chose the following target interface configuration for 
<a class="code2model" id="code2model" href="matlab:Simulink.ID.hilite('OFDM_Tx_HW')">OFDM_Tx_HW</a>
:
<br/><br/>
Processor/FPGA synchronization mode: 
<b>Free running</b>
<br/><br/>
Target platform interface table:
<br/>
<table>
<thead class="reportTableHeader">
<tr>
<td>Port Name
</td>
<td>Port Type
</td>
<td>Data Type
</td>
<td>Target Platform Interfaces
</td>
<td>Bit Range / Address / FPGA Pin
</td>
</tr>
</thead>
<tbody>
<tr>
<td><a class="code2model" id="code2model" href="matlab:Simulink.ID.hilite('OFDM_Tx_HW:9874')">modScheme</a>
</td>
<td>Inport
</td>
<td>uint32
</td>
<td>AXI4-Lite
</td>
<td>x"100"
</td>
</tr>
<tr>
<td class="distinctCellColor"><a class="code2model" id="code2model" href="matlab:Simulink.ID.hilite('OFDM_Tx_HW:9875')">enable</a>
</td>
<td class="distinctCellColor">Inport
</td>
<td class="distinctCellColor">boolean
</td>
<td class="distinctCellColor">AXI4-Lite
</td>
<td class="distinctCellColor">x"104"
</td>
</tr>
<tr>
<td><a class="code2model" id="code2model" href="matlab:Simulink.ID.hilite('OFDM_Tx_HW:9876')">gain</a>
</td>
<td>Inport
</td>
<td>uint32
</td>
<td>AXI4-Lite
</td>
<td>x"108"
</td>
</tr>
<tr>
<td class="distinctCellColor"><a class="code2model" id="code2model" href="matlab:Simulink.ID.hilite('OFDM_Tx_HW:10147')">data</a>
</td>
<td class="distinctCellColor">Outport
</td>
<td class="distinctCellColor">uint32
</td>
<td class="distinctCellColor">AXI4-Stream Master
</td>
<td class="distinctCellColor">Data
</td>
</tr>
<tr>
<td><a class="code2model" id="code2model" href="matlab:Simulink.ID.hilite('OFDM_Tx_HW:10148')">valid</a>
</td>
<td>Outport
</td>
<td>boolean
</td>
<td>AXI4-Stream Master
</td>
<td>Valid
</td>
</tr>
</tbody>
</table>
</div>
<div>
<h3 class="sectionHeading">Register Address Mapping</h3>
The following AXI4-Lite bus accessible registers were generated for this IP core:
<br/><br/>
<table>
<thead class="reportTableHeader">
<tr>
<td>Register Name
</td>
<td>Address Offset
</td>
<td>Description
</td>
</tr>
</thead>
<tbody>
<tr>
<td>IPCore_Reset
</td>
<td>0x0
</td>
<td>write 0x1 to bit 0 to reset IP core
</td>
</tr>
<tr>
<td class="distinctCellColor">IPCore_Enable
</td>
<td class="distinctCellColor">0x4
</td>
<td class="distinctCellColor">enabled (by default) when bit 0 is 0x1
</td>
</tr>
<tr>
<td>IPCore_PacketSize_AXI4_Stream_Master
</td>
<td>0x8
</td>
<td>Packet size for AXI4-Stream Master interface, the default value is 1024. The TLAST output signal of the AXI4-Stream Master interface is generated based on the packet size.
</td>
</tr>
<tr>
<td class="distinctCellColor">IPCore_Timestamp
</td>
<td class="distinctCellColor">0xC
</td>
<td class="distinctCellColor">contains unique IP timestamp (yymmddHHMM): 2203242151
</td>
</tr>
<tr>
<td>modScheme_Data
</td>
<td>0x100
</td>
<td>data register for Inport modScheme
</td>
</tr>
<tr>
<td class="distinctCellColor">enable_Data
</td>
<td class="distinctCellColor">0x104
</td>
<td class="distinctCellColor">data register for Inport enable
</td>
</tr>
<tr>
<td>gain_Data
</td>
<td>0x108
</td>
<td>data register for Inport gain
</td>
</tr>
</tbody>
</table>
<br/>
The AXI4 slave write register readback is ON for the IP core.
<br/>
The register address mapping is also in the following C header file for you to use when programming the processor:
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\include\ofdm_tx_addr.h')">include\ofdm_tx_addr.h</a>
<br/>
The IP core name is appended to the register names to avoid name conflicts.
</div>
<div>
<h3 class="sectionHeading">IP Core User Guide</h3>
<b>Theory of Operation</b>
<br/><br/>
This IP core is designed to be connected to an embedded processor with an 
<b>AXI4-Lite interface. </b>
The processor acts as master, and the IP core acts as slave. By accessing the generated registers via the AXI4-Lite interface, the processor can control the IP core, and read and write data from and to the IP core. 
<br/><br/>
For example, to reset the IP core, write 0x1 to the bit 0 of IPCore_Reset register. To enable or disable the IP core, write 0x1 or 0x0 to the IPCore_Enable register. To access the data ports of the MATLAB/Simulink algorithm, read or write to the associated data registers.
<br/><br/>
<img src="doc_arch_axi4_lite_stream.jpg"/>
<br/><br/>
This IP core also includes the AXI4-Stream interfaces 
<b>AXI4-Stream Master. </b>
The AXI4-Stream interfaces can be connected to the processor via a DMA controller, or they can be connected to other IP cores with AXI4-Stream interfaces. For example, the diagram above shows a design using AXI4-Stream interfaces as the data path, and using AXI4-Lite interface as the control path. 
<br/><br/>
The AXI4 Slave port to pipeline register ratio selected as 35 in task 3.2 for this model. The default delay to read AXI4 register is one clock cycle.
Depending on the selected ratio and IO connected to AXI4 interface, register pipelining is introduced in the read logic of AXI4 registers.
For your model AXI4 pipeline register ratio setting 35 is larger than all the readable AXI4 slave registers. Total readable AXI4 slave registers are 6, so no pipelining is added to the AXI4 register read back logic.
<br/><br/>
<b>Processor/FPGA Synchronization</b>
<br/><br/>
The 
<b>Free running </b>
mode means there is no explicit synchronization between embedded processor software execution (SW) and the IP core (HW). SW and HW runs independently. The data written from the processor to IP core takes effect immediately, and the data read from the IP core is the latest data available on the IP core output ports. 
<br/><br/>
<img src="free_running.jpg"/>
<br/><br/>
<b>Xilinx Vivado Environment Integration</b>
<br/><br/>
This IP Core is generated for the Xilinx Vivado environment. The following steps are an example showing how to integrate the generated IP core into Xilinx Vivado environment:
<br/><br/>
1. The generated IP core is a zip package file under the IP core folder. Please check the Summary section of this report for the IP zip file name and folder.
<br/>
2. In the Vivado project, go to Project Settings -> IP -> Repository Manager, add the folder containing the IP zip file as IP Repository.
<br/>
3. In Repository Manger, click the "Add IP" button to add IP zip file to the IP repository. This step adds the generated IP into the Vivado IP Catalog.
<br/>
4. In the Vivado project, find the generated IP core in the IP Catalog under category "HDL Coder Generated IP". In you have a Vivado block design open, you can add the generated IP into your block design.
<br/>
5. Connect the AXI4_Lite port of the IP core to the embedded processor's AXI master port.
<br/>
6. Connect the clock and reset ports of the IP core to the global clock and reset signals.
<br/>
7. Assign an Offset Address for the IP core in the Address Editor.
<br/>
8. Connect external ports and add FPGA pin assignment constraints to constraint file.
<br/>
9. Generate FPGA bitstream and download the bitstream to target device.
<br/><br/>
If you are targeting Xilinx Zynq hardwares supported by HDL Coder Support Package for Xilinx Zynq Platform, you can select the board you are using in the Target platform option in the Set Target > Set Target Device and Synthesis Tool task. You can then use Embedded System Integration tasks in HDL Workflow Advisor to help you integrate the generated IP core into Xilinx Vivado environment.
</div>
<div>
<h3 class="sectionHeading">IP Core File List</h3>
The IP core folder is located at:
<br/>
<a href="matlab:uiopen('hdl_prj\ipcore\ofdm_tx_v0_4\*.*')">hdl_prj\ipcore\ofdm_tx_v0_4</a>
<br/>
Following files are generated under this folder:
<br/><br/>
<b>IP core zip file</b>
<br/>
<a href="matlab:uiopen('hdl_prj\ipcore\ofdm_tx_v0_4\*.*')">ofdm_tx_v0_4.zip</a>
<br/><br/>
<b>IP core report</b>
<br/>
<a href="matlab:web('hdl_prj\ipcore\ofdm_tx_v0_4\doc\OFDM_Tx_HW_ip_core_report.html')">doc\OFDM_Tx_HW_ip_core_report.html</a>
<br/><br/>
<b>IP core HDL source files</b>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_OFDMTx_pkg.vhd')">hdl\vhdl\ofdm_tx_src_OFDMTx_pkg.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_DualPortRAM_generic.vhd')">hdl\vhdl\ofdm_tx_src_DualPortRAM_generic.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_READ_CTRL2.vhd')">hdl\vhdl\ofdm_tx_src_READ_CTRL2.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_DataExtend.vhd')">hdl\vhdl\ofdm_tx_src_DataExtend.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_LTFValidGen.vhd')">hdl\vhdl\ofdm_tx_src_LTFValidGen.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_READ_CTRL.vhd')">hdl\vhdl\ofdm_tx_src_READ_CTRL.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_LTFExtend.vhd')">hdl\vhdl\ofdm_tx_src_LTFExtend.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_STFValidGen.vhd')">hdl\vhdl\ofdm_tx_src_STFValidGen.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_READ_CTRL_block.vhd')">hdl\vhdl\ofdm_tx_src_READ_CTRL_block.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_STFExtend.vhd')">hdl\vhdl\ofdm_tx_src_STFExtend.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_Mux2.vhd')">hdl\vhdl\ofdm_tx_src_Mux2.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_CPAdd.vhd')">hdl\vhdl\ofdm_tx_src_CPAdd.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RisingEdge.vhd')">hdl\vhdl\ofdm_tx_src_RisingEdge.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PreamValidGen.vhd')">hdl\vhdl\ofdm_tx_src_PreamValidGen.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_dataReadyGen.vhd')">hdl\vhdl\ofdm_tx_src_dataReadyGen.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_dataValidGen.vhd')">hdl\vhdl\ofdm_tx_src_dataValidGen.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_pilotValidGen.vhd')">hdl\vhdl\ofdm_tx_src_pilotValidGen.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_ControlSignalGenerator.vhd')">hdl\vhdl\ofdm_tx_src_ControlSignalGenerator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_LTSfreq.vhd')">hdl\vhdl\ofdm_tx_src_LTSfreq.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_ToComplex1.vhd')">hdl\vhdl\ofdm_tx_src_ToComplex1.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PilotGen.vhd')">hdl\vhdl\ofdm_tx_src_PilotGen.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator.vhd')">hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator1.vhd')">hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator1.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator2.vhd')">hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator2.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator3.vhd')">hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator3.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator4.vhd')">hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator4.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator5.vhd')">hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator5.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator6.vhd')">hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator6.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator7.vhd')">hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator7.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator8.vhd')">hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator8.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator9.vhd')">hdl\vhdl\ofdm_tx_src_PN_Sequence_Generator9.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_Subsystem.vhd')">hdl\vhdl\ofdm_tx_src_Subsystem.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_Random_Generator.vhd')">hdl\vhdl\ofdm_tx_src_Random_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_8PSK_Generator.vhd')">hdl\vhdl\ofdm_tx_src_8PSK_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_BPSK_Generator.vhd')">hdl\vhdl\ofdm_tx_src_BPSK_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_im1.vhd')">hdl\vhdl\ofdm_tx_src_complement_im1.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_re1.vhd')">hdl\vhdl\ofdm_tx_src_complement_re1.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_QAM1024_Generator.vhd')">hdl\vhdl\ofdm_tx_src_QAM1024_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement.vhd')">hdl\vhdl\ofdm_tx_src_complement.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_im.vhd')">hdl\vhdl\ofdm_tx_src_complement_im.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_re.vhd')">hdl\vhdl\ofdm_tx_src_complement_re.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_QAM128_Generator.vhd')">hdl\vhdl\ofdm_tx_src_QAM128_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_QAM16_Generator.vhd')">hdl\vhdl\ofdm_tx_src_QAM16_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_im_block.vhd')">hdl\vhdl\ofdm_tx_src_complement_im_block.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_re_block.vhd')">hdl\vhdl\ofdm_tx_src_complement_re_block.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_QAM256_Generator.vhd')">hdl\vhdl\ofdm_tx_src_QAM256_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_block.vhd')">hdl\vhdl\ofdm_tx_src_complement_block.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_im_block1.vhd')">hdl\vhdl\ofdm_tx_src_complement_im_block1.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_re_block1.vhd')">hdl\vhdl\ofdm_tx_src_complement_re_block1.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_QAM32_Generator.vhd')">hdl\vhdl\ofdm_tx_src_QAM32_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement2.vhd')">hdl\vhdl\ofdm_tx_src_complement2.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_im2.vhd')">hdl\vhdl\ofdm_tx_src_complement_im2.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_re_block2.vhd')">hdl\vhdl\ofdm_tx_src_complement_re_block2.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_QAM512_Generator.vhd')">hdl\vhdl\ofdm_tx_src_QAM512_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_im_block2.vhd')">hdl\vhdl\ofdm_tx_src_complement_im_block2.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_complement_re_block3.vhd')">hdl\vhdl\ofdm_tx_src_complement_re_block3.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_QAM64_Generator.vhd')">hdl\vhdl\ofdm_tx_src_QAM64_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_QPSK_Generator.vhd')">hdl\vhdl\ofdm_tx_src_QPSK_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_Variable_Modulator.vhd')">hdl\vhdl\ofdm_tx_src_Variable_Modulator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RF_Signal_Generator.vhd')">hdl\vhdl\ofdm_tx_src_RF_Signal_Generator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_STSFreq.vhd')">hdl\vhdl\ofdm_tx_src_STSFreq.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_Data_Multiplexer.vhd')">hdl\vhdl\ofdm_tx_src_Data_Multiplexer.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_DataGenerator.vhd')">hdl\vhdl\ofdm_tx_src_DataGenerator.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_dataIFFTValid.vhd')">hdl\vhdl\ofdm_tx_src_dataIFFTValid.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_preambIFFTValid.vhd')">hdl\vhdl\ofdm_tx_src_preambIFFTValid.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_IFFTValid.vhd')">hdl\vhdl\ofdm_tx_src_IFFTValid.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_SimpleDualPortRAM_generic.vhd')">hdl\vhdl\ofdm_tx_src_SimpleDualPortRAM_generic.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_SDFCommutator1.vhd')">hdl\vhdl\ofdm_tx_src_SDFCommutator1.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX22FFT_SDF1_1.vhd')">hdl\vhdl\ofdm_tx_src_RADIX22FFT_SDF1_1.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX22FFT_CTRL1_1.vhd')">hdl\vhdl\ofdm_tx_src_RADIX22FFT_CTRL1_1.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_SDFCommutator2.vhd')">hdl\vhdl\ofdm_tx_src_SDFCommutator2.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX22FFT_SDF2_2.vhd')">hdl\vhdl\ofdm_tx_src_RADIX22FFT_SDF2_2.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX22FFT_CTRL1_2.vhd')">hdl\vhdl\ofdm_tx_src_RADIX22FFT_CTRL1_2.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_TWDLROM_3_1.vhd')">hdl\vhdl\ofdm_tx_src_TWDLROM_3_1.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_Complex3Multiply.vhd')">hdl\vhdl\ofdm_tx_src_Complex3Multiply.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_SDFCommutator3.vhd')">hdl\vhdl\ofdm_tx_src_SDFCommutator3.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX22FFT_SDF1_3.vhd')">hdl\vhdl\ofdm_tx_src_RADIX22FFT_SDF1_3.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX22FFT_CTRL1_3.vhd')">hdl\vhdl\ofdm_tx_src_RADIX22FFT_CTRL1_3.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_SDFCommutator4.vhd')">hdl\vhdl\ofdm_tx_src_SDFCommutator4.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX22FFT_SDF2_4.vhd')">hdl\vhdl\ofdm_tx_src_RADIX22FFT_SDF2_4.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX22FFT_CTRL1_4.vhd')">hdl\vhdl\ofdm_tx_src_RADIX22FFT_CTRL1_4.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_TWDLROM_5_1.vhd')">hdl\vhdl\ofdm_tx_src_TWDLROM_5_1.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_Complex3Multiply_block.vhd')">hdl\vhdl\ofdm_tx_src_Complex3Multiply_block.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_SDFCommutator5.vhd')">hdl\vhdl\ofdm_tx_src_SDFCommutator5.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX22FFT_SDF1_5.vhd')">hdl\vhdl\ofdm_tx_src_RADIX22FFT_SDF1_5.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX22FFT_CTRL1_5.vhd')">hdl\vhdl\ofdm_tx_src_RADIX22FFT_CTRL1_5.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_SDFCommutator6.vhd')">hdl\vhdl\ofdm_tx_src_SDFCommutator6.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX22FFT_SDF2_6.vhd')">hdl\vhdl\ofdm_tx_src_RADIX22FFT_SDF2_6.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX22FFT_CTRL1_6.vhd')">hdl\vhdl\ofdm_tx_src_RADIX22FFT_CTRL1_6.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_RADIX2FFT_bitNatural.vhd')">hdl\vhdl\ofdm_tx_src_RADIX2FFT_bitNatural.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_IFFT_HDL_Optimized.vhd')">hdl\vhdl\ofdm_tx_src_IFFT_HDL_Optimized.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_IFFT.vhd')">hdl\vhdl\ofdm_tx_src_IFFT.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_READ_CTRL2_block.vhd')">hdl\vhdl\ofdm_tx_src_READ_CTRL2_block.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_DataMapper.vhd')">hdl\vhdl\ofdm_tx_src_DataMapper.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_READ_CTRL_block1.vhd')">hdl\vhdl\ofdm_tx_src_READ_CTRL_block1.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_PremableMapper.vhd')">hdl\vhdl\ofdm_tx_src_PremableMapper.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_Mux2_block.vhd')">hdl\vhdl\ofdm_tx_src_Mux2_block.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_SCMapper.vhd')">hdl\vhdl\ofdm_tx_src_SCMapper.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_OFDMTx_tc.vhd')">hdl\vhdl\ofdm_tx_src_OFDMTx_tc.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_src_OFDMTx.vhd')">hdl\vhdl\ofdm_tx_src_OFDMTx.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_reset_sync.vhd')">hdl\vhdl\ofdm_tx_reset_sync.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_dut.vhd')">hdl\vhdl\ofdm_tx_dut.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_SimpleDualPortRAM_generic.vhd')">hdl\vhdl\ofdm_tx_SimpleDualPortRAM_generic.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_fifo_data_OUT.vhd')">hdl\vhdl\ofdm_tx_fifo_data_OUT.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_SimpleDualPortRAM_singlebit.vhd')">hdl\vhdl\ofdm_tx_SimpleDualPortRAM_singlebit.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_fifo_TLAST_OUT.vhd')">hdl\vhdl\ofdm_tx_fifo_TLAST_OUT.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_axi4_stream_master.vhd')">hdl\vhdl\ofdm_tx_axi4_stream_master.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_addr_decoder.vhd')">hdl\vhdl\ofdm_tx_addr_decoder.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_axi_lite_module.vhd')">hdl\vhdl\ofdm_tx_axi_lite_module.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx_axi_lite.vhd')">hdl\vhdl\ofdm_tx_axi_lite.vhd</a>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\hdl\vhdl\ofdm_tx.vhd')">hdl\vhdl\ofdm_tx.vhd</a>
<br/>
<br/>
<b>IP core C header file</b>
<br/>
<a href="matlab:edit('hdl_prj\ipcore\ofdm_tx_v0_4\include\ofdm_tx_addr.h')">include\ofdm_tx_addr.h</a>
</div>
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